The present invention relates generally to flash memory cell devices and more specifically, to improvements in dielectric memory cell structures for dual bit storage and a process for making the improved dielectric memory cell structure.
Conventional floating gate flash memory types of EEPROMs (electrically erasable programmable read only memory), utilize a memory cell characterized by a vertical stack of a tunnel oxide (SiO2), a polysilicon floating gate over the tunnel oxide, an interlayer dielectric over the floating gate (typically an oxide, nitride, oxide stack), and a control gate over the interlayer dielectric positioned over a crystalline silicon substrate. Within the substrate are a channel region positioned below the vertical stack and source and drain diffusions on opposing sides of the channel region.
The floating gate flash memory cell is programmed by inducing hot electron injection from the channel region to the floating gate to create a non volatile negative charge on the floating gate. Hot electron injection can be achieved by applying a drain to source bias along with a high control gate positive voltage. The gate voltage inverts the channel while the drain to source bias accelerates electrons towards the drain. The accelerated electrons gain 5.0 to 6.0 eV of kinetic energy which is more than sufficient to cross the 3.2 eV Sixe2x80x94SiO2 energy barrier between the channel region and the tunnel oxide. While the electrons are accelerated towards the drain, those electrons which collide with the crystalline lattice are re-directed towards the Sixe2x80x94SiO2 interface under the influence of the control gate electrical field and gain sufficient energy to cross the barrier.
Once programmed, the negative charge on the floating gate increases the threshold voltage of the FET characterized by the source region, drain region, channel region, and control gate. During a xe2x80x9creadxe2x80x9d of the memory cell, the magnitude of the current flowing between the source and drain at a predetermined control gate voltage indicates whether the flash cell is programmed.
More recently dielectric memory cell structures have been developed. A conventional dielectric memory cell 10 is shown in cross section in FIG. 1 and is characterized by a vertical stack of an insulating tunnel dielectric layer 12, a charge trapping dielectric layer 14, an insulating top oxide layer 16, and a polysilicon control gate 18 positioned on top of a crystalline silicon substrate 15. Within the substrate 15 are a channel region 17 positioned below the vertical stack and source diffusion 19 and drain diffusion 23 on opposing sides of the channel region 17. This particular structure of a silicon channel region 22, tunnel oxide 12, nitride 14, top oxide 16, and polysilicon control gate 18 is often referred to as a SONOS device.
Similar to the floating gate device, the SONOS memory cell 10 is programmed by inducing hot electron injection from the channel region 17 to the nitride layer 14 to create a non volatile negative charge within charge traps existing in the nitride layer 14. Again, hot electron injection can be achieved by applying a drain-to-source bias along with a high positive voltage on the control gate 18. The high voltage on the control gate 18 inverts the channel region 17 while the drain-to-source bias accelerates electrons towards the drain region 23. The accelerated electrons gain 5.0 to 6.0 eV of kinetic energy which is more than sufficient to cross the 3.2 eV Sixe2x80x94SiO2 energy barrier between the channel region 17 and the tunnel oxide 12. While the electrons are accelerated towards the drain region 23, those electrons which collide with the crystalline lattice are re-directed towards the Sixe2x80x94SiO2 interface under the influence of the control gate electrical field and have sufficient energy to cross the barrier. Because the nitride layer stores the injected electrons within traps and is otherwise a dielectric, the trapped electrons remain localized within a drain charge storage region 13 that is close to the drain region 23 (or in a source charge storage region 11 that is close to the source region 19 if a source to drain bias is used) from which the electrons were injected. As such, the SONOS device can be used to store two bits of data, one in each of the charge storage regions 11 and 13, per cell and are typically referred to as dual bit SONOS devices.
A problem associated with dual bit SONOS structures is that the trapped charge in the drain and source charge storage regions 13 and 11 has a finite spatial distribution that peaks at the drain region 23 and source region 19 respectively and a portion of the charge distribution will spread into the area between the source charge storage region 11 and the drain charge storage region 13. The spread charge effects the threshold voltage during the read cycle. The charge that accumulates between the source charge storage region 11 and the drain charge storage region 13 is difficult to remove utilizing the hot hole injection erase mechanism. Additionally, charge spreading become more problematic over the lifetime of operation of the device. Each program/erase cycle, may cause further spread of electrons into the area between source charge storage region 11 and the drain charge storage region 13. The problem is further compounded by the continued decrease in the size of the semiconductor devices, which calls for nitride layers with less area separating the two charge storage regions 11 and 13.
A need exists in the art for a dual bit memory cell structure which does not suffer the disadvantages discussed above.
A first aspect of the present invention is to provide a dual bit dielectric memory cell that comprises a substrate with a source region, a drain region, and a channel region positioned there between. A multilevel charge trapping dielectric is positioned on the surface of the substrate over the channel region and a control gate is positioned on the surface of the multilevel charge trapping dielectric. The multilevel charge trapping dielectric includes a tunnel layer adjacent to the substrate that may comprise a dielectric material with a very low hydrofluoric acid etch rate. The multilevel charge trapping dielectric also includes a top dielectric layer adjacent to the control gate of a second dielectric material selected from the group consisting of an aluminum oxide compound, a Hafnium oxide compound, and a zirconium oxide compound. Such materials may comprise Al2O3, HfSiOx, HfO2, and ZrO2.
A charge trapping layer is positioned between the tunnel layer and the top dielectric layer and includes a source charge trapping region and a drain charge trapping region separated by an isolation barrier, that may be an oxide, there between. The charge trapping layer may have a thickness range from about 50 A to 100 A in thickness.
The source charge trapping region and the drain charge trapping region may be comprised of a nitride compound such as a material selected from the group consisting of Si2N4 and SiOxN4. The source charge trapping region and the drain charge trapping region may each have a lateral width beneath the top dielectric layer from about 300 A to 500 A.
A second aspect of the present invention is to provide a method of storing data in dual bit dielectric memory cell, the method comprising: a) utilizing a source-to-drain bias in the presence of a control gate field to inject a charge into a source charge trapping region; b) utilizing a drain-to-source bias in the presence of a control get field to inject a charge into a drain charge trapping region; and c) providing an isolation barrier between the source charge trapping region and the drain charge trapping region.
A third aspect of the invention provides a method for making the dielectric memory cell structure, including steps of providing a semiconductor substrate; sequentially depositing on the substrate a first dielectric material, an oxide layer, a second dielectric material with a dielectric constant equal to or greater than the first dielectric material, and a polysilicon control gate; isotropically etching the oxide layer with HF acid to open spaces beneath the second dielectric material; and depositing a nitride charge trapping layer within the open spaces beneath the second dielectric material.
A fourth aspect of the present invention is to provide a process for fabricating a dual bit dielectric memory cell structure with an isolation barrier between two charge trapping dielectric regions.
The method comprises implanting buried bit lines within a substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer.
A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material, such as silicon nitride, is deposited within the undercut region.
The tunnel dielectric layer may comprise a material with a low hydrofluoric acid etch rate. As such, removing a portion of the isolation barrier dielectric layer to form an undercut region within the gate region may comprising performing an isotropic etch using dilute hydrofluoric acid. The charge trapping material may be deposited within the undercut region by depositing a layer of silicon nitride compound on the surface of the wafer using a vapor deposition process and by performing an anisotropic etch to remove the layer of the silicon nitride compound from the horizontal surfaces.
The layered island may be formed on the surface of the substrate by: a) depositing a tunnel dielectric layer on the surface of the substrate; b) depositing an isolation barrier dielectric layer on the surface of the tunnel dielectric layer; c) depositing a top dielectric layer on the surface of the isolation barrier dielectric layer; d) depositing a polysilicon gate layer on the surface of the top dielectric layer; e) masking a gate pattern on the surface of the polysilicon gate layer to define a gate region and expose a non-gate region; and f) removing the polysilicon gate layer, the top dielectric layer, the isolation barrier dielectric layer and the tunnel dielectric layer in the non-gate region.